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TSMC: SRAM cache for the CPU and GPU has reached the limits of scaling processor cache will stop growing quickly, and development will rise Aroged, Aroged

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The 68th annual IEEE International Electron Devices Meeting (IEDM) is coming back in full force, in San Francisco, where almost 1 500 engineers from around the world can meet in person.

Among the many materials that had a hard and applied nature in the industry to study the current trend, the most resonant report was published in the journal TSMC in which the study proposed scaling the density of SRAM cache memory. Shortly enough, he stopped. While the process logic continues to have considerable scaling impact, the technology used in the industry can no longer significantly increase the speed of SRAM.

At the conference, TSMC talked about the origin of the base node N3B and the new version of N3E. Interestingly, for the new N3E node, the high-density SRAM bit cell size has not been reduced at all. The Bit Cell area is 0.021 m exactly the same as the N5 node. The N3B variant isn’t expected to be used by most of the products, but has a smaller SRAM cell with a 0.0199m drop compared to the N5 process technology. The approximate memory density of the N3E is approximately thirty-sixty-nine oz and can equate to thirty-five and seven-two, six-ty-five oz, or more.

To show the dynamics and possibilities of processor development into perspective, note that while the N3B and N3E deliver 1.6, and 1,7, chip-level transistor scaling, SRAM scaling is only 1-1,05. We can still expect that TSMC will continue building denser SRAM bit cells for the N3 if it does, but there will never be significant changes along the way.

SRAM scaling slowdown is not just limited to TSMC. The problem has been around for a long time. Intel is still able to downscale SRAM cell density, yet, in the recently announced Intel 4 process technology, SRAM scaling has slowed to 0.50-0.8x.

Impact of Stopping SRAM Scaling on Processor Design in the SRAM Projector Impacts.

At present, the only viable alternative to scaling SRAM is to simply increase the number of caches that could be captured by the ccc will take up more space. This reduces the cost of manufacturing equipment and prevents it from becoming as small as they are. The physical limitation of cache scaling is becoming a significant factor that influenced future architectures to design.

Most processors use caches as storage solutions with low access times due to their strategic location around the compute cores. Having a fast, accessible storage can greatly improve the processing performance and reduce the amount of time needed to do their job. Because of the slowness in development of caching technology, performance is obstructed.

Future perspectives and alternatives for improving Cache Memory: Future Perspectives and Alternatives to Improving Cache Memory.

Some research institutes such as Imec have already introduced higher density SRAM cells. In 2017, in 2021, Imec announced a SRAM density of about 60 mmm. The current density is about double the value of an hypothetical node above 2nm.

The industry also explored a variety of other memory architectures. Most of them are MRAM, FeRAM, NRAM, RRAM, STT-RAM, PCM and others technologies. These new bit memory cells offer unique advantages over SRAM: higher density and lower read/write performance, non-volatility capability, faster read/write cycles or less energy consumption.

Although these technologies aren’t direct replacement for SRAM, future use could be used to create cache memory at the fourth or fifth level in order to compensate performance for the high density of the performance loss.

Sources: WikiChip Fuse, TechSpot.


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